1. Field of the Invention
The present invention relates to a semiconductor device suitable for very large scale integration and a manufacturing method thereof.
2. Description of the Related Art
A DRAM (Dynamic Random Access Memory) is roughly defined into a memory cell array part having a memory cell array provided therein, a peripheral circuit part having drive circuits of memory cells and so on, and a dicing line part on an outer periphery of a chip. Between the peripheral circuit part and the dicing line part, a guard ring part is provided for the purpose of preventing moisture intrusion from the outside. Such a DRAM is manufactured by the following method. FIG. 25 to FIG. 30 are sectional views showing a manufacturing method of a semiconductor device in a prior art in the order of its steps.
First, as shown in FIG. 25, element isolation regions 112 are formed on a surface of a semiconductor substrate 111 through a generally known STI (Shallow Trench Isolation) process. Thereafter, ion implantation for forming wells, a channel stop diffusion layer (neither is shown), and so on is carried out. Next, a gate oxide film 113 is formed. Thereafter, a polycrystalline Si film and a WSi film are deposited in sequence, over which a SiN film and so on to be an insulation film layer are further deposited. Next, formation of a resist film, patterning of the resist film, and etching are conducted so that wiring layers 114 each constituted of a polycrystalline Si film 114a and a WSi film 114b, and a SiN film 145 are formed.
Next, ion implantation for forming an LDD (Lightly Doped Drain) structure is carried out to form a diffusion layer 115. Next, sidewalls 116 comprising Si3N4 are formed. Next, an interlayer insulation film 117 comprising BPSG (Boron-Phospho Silicate Glass) and TEOS (Tetra Ethyl Ortho Silicate) is deposited over the entire surface and reflow of this interlayer insulation film 117 is carried out. This reflow is carried out at a temperature of 800° C. in the atmosphere of N2 for 20 minutes. Then, the interlayer insulation film 117 is planarized by a CMP (Chemical Mechanical Polishing) method or the like. The foregoing steps are MOSFET forming steps in generally known DRAM manufacturing technology.
Subsequently, as shown in FIG. 25, the interlayer insulation film 117 is patterned so that contact holes 118 for establishing contact with source/drain regions of cell transistors provided on the semiconductor substrate 111, namely, with the diffusion layer 115 in the memory cell array part 101, are formed in the interlayer insulation film 117. This patterning can be performed by SAC (Self Align Contact) etching since etching selectivity between the interlayer insulation film 117 and the sidewalls 116 is high.
Next, as shown in FIG. 26, a polycrystalline Si film is buried in each of the contact holes 118, and this polycrystalline Si film is polished by CMP until the interlayer insulation film 117 is exposed so that conductive plugs 119 are formed. Next, an HTO film (High Temperature Oxide film) is deposited over the entire surface as an interlayer insulation film 120.
Thereafter, a photoresist (not shown) is formed over the entire surface. Openings are formed at respective portions of this photoresist corresponding to bit contact portions of the memory cell array part 101, source/drain contact portions of MOSFETs in the peripheral circuit part 102, and gate portions of the MOSFETs in the peripheral circuit part 102. At the same time, openings are formed at a portion thereof corresponding to a ring-shaped diffusion layer 115 in the guard ring part 104. Then, using this photoresist as a mask, the interlayer insulation films 120 and 117 are etched. Consequently, as shown in FIG. 26, contact holes 121 to 123 are formed, and a ring-shaped trench 147 reaching the diffusion layer 115 is also formed in the guard ring part 104. The contact holes 121 are formed at the bit contact portions in the memory cell array part 101, the contact holes 122 are formed at the source/drain contact portions of the MOSFETs in the peripheral circuit part 102, and the contact holes 123 are formed in the gate portions of the MOSFETs in the peripheral circuit part 102. Incidentally, the contact holes 122 are also formed at other portions, though not shown, requiring substrate contact, such as diffusion layer resistances and so on in the peripheral circuit part 102.
Subsequently, as shown in FIG. 27, the source/drain portions and the portions requiring the substrate contact such as the diffusion layer resistances inside the peripheral circuit part 102 undergo ion implantation for contact stabilization in the peripheral circuit part 102 between the semiconductor substrate 111 (diffusion layer 115) and wiring layers to be formed thereafter comprising refractory metal. Then, in order to activate implanted impurities, furnace annealing or RTA (Rapid Thermal Annealing) such as ramp annealing is conducted. The temperature of this high-temperature annealing is set to about 1000° C.
Next, a barrier metal film 124 constituted of a layer of a Ti film and a TiN film, a W wiring layer 125, and a SiON film 126 as an antireflection film are deposited, Thereafter, a photoresist (not shown) is formed and openings are formed in this photoresist. Subsequently, using this photoresist film as a mask, the wiring layer 125 is etched. Incidentally, in some cases, the SiON film 126 is not formed. Next, as shown in FIG. 27, a pressure-reduced SiN film 127 is deposited by a pressure-reduced CVD method, and the wiring layer 125 is covered with the pressure-reduced SiN film 127.
Thereafter, as shown in FIG. 28, a high-density plasma oxide film (HDP film) is deposited over the entire surface as an interlayer insulation film 128, and the interlayer insulation film 128 is planarized by a planarization technique such as CMP.
Subsequently, a SiN film 129 is deposited. Next, storage-side holes 130 of the cells are formed by a generally known contact forming method through PSC (Poly Shrunk Contact), and contact plugs 131 are buried in these storage-side holes 130.
Next, cylindrical storage electrodes 132 are formed on the interlayer insulation film 128 by a generally known cylinder forming method. Subsequently, after a SiN film and an oxide film to be a capacitor dielectric film 133 are formed by a CVD method, opposing electrodes 134 comprising doped amorphous Si are formed.
Then, as shown in FIG. 28, an insulation film such as an HDP film is deposited as an interlayer insulation film 135 after capacitors are formed. Thereafter, this interlayer insulation film 135 is planarized using a planarization technique such as CMP.
Next, as shown in FIG. 29, contact holes 136 reaching a part of the wiring layers 125 are formed in the peripheral circuit part 102 while, in the guard ring part 104, a ring-shaped trench 137 reaching the wiring layer 125 is formed. This means that the contact holes 136 and the trench 137 are formed concurrently. At this time, contact holes, though not shown, reaching a part of the wiring layers 114 or wiring layers (not shown) positioned above the wiring layers 114 are concurrently formed as well. Next, barrier metal films 138 are formed in the contact holes 136 and the trench 137, and further, contact plugs 139 are buried therein.
Thereafter, as shown in FIG. 30, while an interlayer insulation film 142, contact holes 143, and so on are being formed, multiple layers of upper wiring layers 140, contact plugs 144, and barrier metal films 141 thereof are formed. Then, an HDP film and a SiN film (not shown) to be a cover film are deposited to complete the DRAM (semiconductor device).
In such a DRAM manufacturing method, however, the interlayer insulation film 117 suffers heat shrinkage at the time of the annealing after the contact holes 121 to 123 are formed, the heat shrinkage starting from the trench 147 in the guard ring (moisture resistant ring) part 104 provided so as to surround the memory cell array part 101 and the peripheral circuit part 102, as shown in FIG. 31. This heat shrinkage causes the deformation of the contact holes 121 to 123 near the trench 147. The amount of this deformation is larger as a contact hole is deeper. Therefore, the contact holes 122 reaching the semiconductor substrate 111 have the largest deformation amount. The occurrence of such contact hole deformation is liable to cause connection failure in the deformed contact holes. If the distances between the trench 147 and all the contact holes 121 to 123 were set to unconditionally large values, the deformation of the contact holes 121 to 123 might be prevented, but this would hinder scale-down of the semiconductor device.
Even if high-temperature annealing is sufficiently applied, for example, at 1000° C. for five seconds before the contact holes 121 to 123 are formed, the interlayer insulation film 117 similarly suffers heat shrinkage when it undergoes another heat treatment after these contact holes are formed.
Accordingly, with the intention of solving such a disadvantage, a semiconductor device in which a guard ring is provided not only on a boundary between a peripheral circuit part and a dicing line part but also on an inner side thereof is disclosed in Japanese Patent Application Laid-open No. 2002-134506. This patent application also discloses that a plurality of guard rings are discontinuously provided. This patent application describes that the above structure enables reduction in a heat shrinkage amount of an interlayer insulation film to improve reliability.
Nevertheless, the contact hole deformation cannot be prevented by the invention described in the Japanese Patent Application Laid-open No. 2002-134506 mentioned above, either. This is because of the following reasons.
Firstly, even if not only the guard ring is provided on the boundary between the peripheral circuit part and the dicing line part, but also the second guard ring is formed on the inner side thereof as a buffer layer with the intention of preventing shrinkage, the same phenomenon as in the case of the first guard ring disposed on the boundary may possibly occur depending on the arrangement of the second guard ring. Namely, the contact hole deformation is caused due to the occurrence of heat shrinkage starting from the second guard ring.
Secondly, as for the divided guard ring, the shrinkage of the interlayer insulation film cannot be prevented even when simply divided portions of the guard ring are arranged.
When the guard ring having such a complicate structure as described in the Japanese Patent Application Laid-open No. 2002-134506 is provided, a problem of the increase in chip area is posed. Specifically, when the guard ring structure is made more complicated than that used before, an additional region for forming the guard ring needs to be provided. This results in restriction on large-scale integration and a lower degree of design (process) freedom.